System having a configurable cache/sram memory
作者： Moinul Syed , Michael Allen , William C. Anderson , Hebbalalu S. Ramagopal , Lawrence A. Booth
DOI:
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摘要: An apparatus having a core processor and memory system is disclosed. The includes at least one data port. connected in such way as to provide substantially simultaneous accesses through the can be made user configurable appropriate model.
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