Control of gate—Drain avalanche in GaAs MESFET's

摘要: The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, output power GaAs FET's. In this paper we show that recognition role surface depletion proper attention to channel design can yield factors 2-3 above bulk values. appropriate strategy is minimization undepleted epitaxial charge per unit area (Q u ) between gate drain, which, in turn, dictates a gate-notch depth approximately equal zero-bias depth. A simple lateral spreading model proposed which predicts V_{L} \sim 50Q\min{u}\max{-1} , where V L Q measured units 1012electrons/cm2. This prediction supported by large body experimental dc pulse data, although considerable scatter observed have attributed epi nonuniformities, premature at rough edges AI gates formed liftoff process, charging variations associated with dielectric passivation. dependence rather than doping level, as predicted for avalanche, provides convincing evidence nonbulk two-dimensional thin-film ( Q_{u} FET geometry. thick films > 2.6 ), other hand, it found predictions are reasonably accurate. terms saturated current I s regime corresponds I_{s} 450 mA/mm (thin-film) mA/mm. Finally, major cause saturation function potential