摘要: A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge hardware-design productivity gap where number of available transistors grows more rapidly than very large scale integration (VLSI) and FPGA computer-aided-design (CAD) tools. ASC addresses this problem a softwarelike programming interface hardware design while keeping performance hand-designed circuits at same time. improves by letting programmer optimize implementation on algorithm level, architecture arithmetic all within C++ program. The increased is applied acceleration wide range applications. Traditionally, accelerators are tediously handcrafted achieve top performance. simplifies design-space exploration transforming task into software-design process, using only "GNU collection (GCC)" "make" obtain netlist. From experience, ease use close pure software development. This paper presents results case studies optimizations that are: 1) level-Kasumi International Data Encryption Algorithm (IDEA) encryptions; 2) level-redundant addition multiplication function evaluation two-dimensional (2-D) rotation; 3) level-Wavelet Lempel-Ziv (LZ)-like compression
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