Fpga configurable logic block with multi-purpose logic/memory circuit
作者： Richard A. Carberry , Ralph D. Wittig , Sundararajarao Mohan
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摘要: A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of programmable device (PLD) that implements an eight-input lookup table (LUT) using array elements arranged rows and columns. decoder is used to read bit values from one column (e.g., sixteen elements) the array. In embodiment, separate line provided facilitate faster operations. sixteen-to-one multiplexer/demultiplexer pass selected output terminal. The both configuration lines during mode, by data transmitted on interconnect resources through circuit. are connected pairs product term generation circuitry. Product terms generated circuitry passed macrocell perform (PAL) another CLB includes four LMCs multiplier such large amounts locally implemented, thereby avoiding signal delays associated with transmission over general purposed within PLD.
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