作者: Masayoshi c , oMatsushita E. I.Co.Ltd Iproc Orihashi , oMatsushita E.I.Co.Ltd Iproc Yoneyama , Morikazu c , oMatsushita E. Ind.Co.Ltd Iproc Sagawa
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摘要: A phase of a sampling clock provided from generating circuit 107 is switched periodically and alternately with difference 180 degrees, during period each phase, timing estimating 105 estimates symbol timing. High-accuracy 109 selects an estimated result higher reliability among results obtained in respective periods, thereby enabling estimation the time resolution twice period. It possible to decrease operation frequency A/D conversion even system requiring synchronization accuracy high accuracy.