Low power logic for statistical inference

摘要: Efficient hardware implementations of statistical inference continue to grow in importance for a wide range computing applications. While CPU cycles are increasingly being used inference, transistors also becoming statistical. For implementing algorithms, could it be that electronic substrates feature rather than bug? We show models can often built from local constraints, and explain the gate-level mathematical functions required resulting solver. suggest signals should consist probabilistic populations particles representing samples probability distribution, with gate acting transform these ensembles. Using this mapping physics we present Bayesian logic circuits as highly efficient alternatives digital standard cell libraries. particular computations, novel VLSI architectures based on consume orders magnitude less power silicon area compared conventional processors.