Area Optimization Based on Graphs of Outputs
作者： Robert Czerwinski , Dariusz Kania
DOI: 10.1007/978-3-642-36166-1_5
关键词:
摘要: A technology-dependent optimization for PAL-based devices based on the analysis of a graph outputs is proposed. This approach oriented to area combinational block FSM. The essence process searching appropriate multi-output implicants that can be shared by several functions. presented uses an original method illustrating minimized form Boolean function. result minimization represented outputs. describes groups multiple-output implicants, which implemented cells.
springer.com
springerlink.com参考文章(11)
Jason Helge Anderson, Stephen Dean Brown, Technology mapping for large complex PLDs design automation conference. pp. 698- 703 ,(1998) , 10.1145/277044.277220
M.J. Ciesielski, S. Yang, PLADE: a two-stage PLA decomposition IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 11, pp. 943- 954 ,(1992) , 10.1109/43.149766
Kenneth Yan, Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks asia and south pacific design automation conference. pp. 231- 234 ,(2001) , 10.1145/370155.370330
Design of Digital Systems and Devices Springer Publishing Company, Incorporated. ,(2014) , 10.1007/978-3-642-17545-9
Dariusz Kania, 6 Efficient Technology Mapping Method for PAL-Based Devices Springer Berlin Heidelberg. pp. 145- 163 ,(2011) , 10.1007/978-3-642-17545-9_6
Martin Bolton, Digital systems design with programmable logic Addison-Wesley Longman Publishing Co., Inc.. ,(1990)
Shih-Liang Chen, TingTing Hwang, C.L. Liu, A technology mapping algorithm for CPLD architectures field-programmable technology. pp. 204- 210 ,(2002) , 10.1109/FPT.2002.1188683
Z. Hasan, D. Harrison, M. Ciesielski, A fast partitioning method for PLA-based FPGAs IEEE Design & Test of Computers. ,vol. 9, pp. 34- 39 ,(1992) , 10.1109/54.173331
L. Wang, A.E.A. Almaini, Optimisation of Reed-Muller PLA implementations IEE Proceedings - Circuits, Devices and Systems. ,vol. 149, pp. 119- 128 ,(2002) , 10.1049/IP-CDS:20020354
Giovanni De Micheli, Synthesis and optimization of digital circuits ,(1994)