Asynchronous/synchronous pipeline dual mode memory access circuit and method
作者： Steven Shyu , David L. Campbell , Jimmy Fung , Jiu An
DOI:
关键词:
摘要: A pipeline memory access circuit has a address buffer for buffering addresses. The first and second pass gate, each of the gates pair complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided selectively switching between an asynchronous synchronous mode operation. includes circuits alternately opening closing when in its operation simultaneously both
lens.org 参考文章(4)
Takashi Shinoda, Masamichi Ishihara, Memory including address registers ,(1988)
Yuichi Miyazawa, Semiconductor memory including transparent latch circuits ,(1987)
Richard H. Womack, Ashwin H. Shah, Chu-Ping Wang, Semiconductor memory with static column decode and page mode addressing capability ,(1986)
John Goodwin Spencer Ive, Alan Clive Thirlwall, Random access memory arrangements ,(1981)