Cache management by the compiler

摘要: An ideal high performance computer includes a fast processor and multi-million byte memory of comparable speed. Since it is currently economically infeasible to have large memories with speeds matching the processor, hardware designers included cache. Because its small size, effectiveness in eliminating speed mismatch, cache has become common feature computers. Enhancing proved be instrumental up cache-based computers. In most cases enhancement methods could classified as either software based, or controlled. cases, based improvement that very effective main were considered inapplicable A reason been cache's transparency programs, response time memory. This resulted only features being considered, implemented for cache. Developments program optimization by compiler successful improving program's performance, understanding behavior. Coupling information about behavior knowledge structure became good approach optimization. With this premise we developed two management models: prompting model, explicit model. Both models rely on underlying concepts of: prefetching, clustering (packing), loop transformations. All three are boosting performance. analyzing these possible implementation found optimal data packing hard problem. Nevertheless, suggested various heuristic packing. We then set forth number conditions The aim transformations facilitate prefetching (preloading) blocks during execution. In both places preload requests within code. These serviced parallel execution. Replacement decisions determined at compile but fully controlled model. model special tag bits introduced each block order replacement decisions. The handling aggregate elements (arrays) also discussed thesis. indexing scheme controlling array access addition, addresses generated load requests, all other