FPGA implementation of an evolving spiking neural network
作者： Alan Zuppicich , Snjezana Soltic
DOI: 10.1007/978-3-642-02490-0_137
关键词:
摘要: This research presents a Field Programmable Gate Array (FPGA) implementation of taste recognition model. The model is based on simple integrate and fire neurons facilitates an on-line learning. whole system, including the hardware required to build (evolve) network was hosted one FPGA chip. used 45% logic elements, 76% memory, 23% dedicated multiplier slices size sufficient for 64 with up synapses each (a total 4096 synapses). proposed successfully applied classification problem at least 10 times faster when evolving 74 during than software simulations executed by stand-alone PC.
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sci-hub.se 参考文章(12)
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