Fixed gating sequence apparatus and method for an inverter

摘要: A fixed gating sequence apparatus and method for an inverter is disclosed. In one aspect of the invention, outgoing signal variable frequency generated by in response to signals provided control. The effectively are a shift register control gates conduction controlled rectifying devices clocking signal. clock input at normal system rate when idle condition (idle signal) not present predetermined cycling from occurs until desired pattern inverter. remains stage providing no longer present, whereupon again register. another aspect, signals, which normally supplied inverter, blocked or inhibited Thus, this does produce moderate burst cycles through stops pattern.