Power control of circuit modules within an integrated circuit
作者： Dele E. Gulick , Larry D. Hewitt , Michael Hogan , David Norris
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摘要: A power control and memory refresh rate management circuit is described. The provides circuitry for selectively disabling or enabling modular logic blocks within a VLSI integrated under program from an external processor, suspended operation in general. In low-power modes signal generation circuits are provided with low-frequency oscillator to conserve power.
lens.org 参考文章(36)
Todd R. Witkowski, Power on reset signal circuit with clock inhibit and delayed reset ,(1994)
Robert L. Bailey, Mike S. Hanlon, R. Steven Smith, Power management for a laptop computer with slow and sleep modes ,(1992)
James R. Macdonald, Clock control for power savings in high performance central processing units ,(1992)
John P. Roesgen, Modulo address generator ,(1987)
Katsunobu Hongo, Clock control circuit ,(1995)
Kenneth A. Lies, Clocked logic low power standby mode ,(1979)
Donald L. Tietjen, Wait mode power reduction system and method for data processor ,(1987)
Terrill M. Moore, Method and apparatus for disabling and restarting clocks ,(1993)
William C. Rempfer, Sammy S. Lum, Software controlled power shutdown in an integrated circuit ,(1993)
Terrie L. Frane, Power saving arrangement for a clocked digital circuit ,(1990)