作者: Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
DOI:
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摘要: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and interface controllers; each IP block adapted to a router through controller controller; at least one also including computer an L1, write-through data cache comprising high speed local the block, controlled by having line replacement policy, configured lock segments of cache, store thread-private in main off further segment L1 locked against upon misses under controller's memory.