Method of in-process intralayer yield detection, interlayer shunt detection and correction
作者： Scott Jong Ho Limb , William S. Wong , Robert A. Street , Michael Yu Tak Young
DOI:
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摘要: A system and method for in-process yield evaluation correction in an array type of device are provided. The include measuring electrical resistance between individual GATE lines, DATA a bus I/O pad, pad; analyzing the measured to identify at least one following: line open defects, bridge interlayer shunt defects.
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