作者: Minhan Chen
DOI:
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摘要: Aspects of the disclosure are directed to determining an offset calibration step size a sample latch. In accordance with one aspect, relate Decision Feedback Equalizer (DFE) input section including E latch output target signal sample; digital analog converter coupled voltage latch; and generate bias voltage, wherein is inputted The DFE may further include decoder scale summing amplifier receive waveform section.