Phase-locked loop circuit
作者： Hirohisa Kikugawa
DOI:
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摘要: A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs a reference signal source (1) and voltage-controlled oscillator (VCO) (3) are frequency-divided by divider circuits (2, 4), respectively. phase comparator (5) is provided for outputting an error indicative difference between these signals, if any. window generator (9) connected signal; where the does not fall within range pulse width signal, level generates boost voltage having its potential near control value VCO use in generating target frequency. low-pass filter (LPF) (7) charged up responding to receipt both output charge pump (6) so that may rapidly increase at without rising any excess values. Whereby, undershoot overshoot be eliminated or least greatly suppressed thus enabling achievement increased
lens.org 参考文章(5)
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