作者: Brian T. Deng , Merril Newman , David E. Kimble
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摘要: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on is operable to receive packet from (140) via receiver (146). Asynchronous and isochronous are stored in FIFO (166) for later use by host interface (150). The verified hardware circuit (170) that provides verification as they received without requiring software evaluate storage (166). If an error determined, this registers (164) processing