Data processor with means for separately receiving and processing different types of interrupts
作者： Toru Shimizu , Shunichi Iwata
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摘要: A data processor which is provided with a flag in Processor Status Word (PSW) 116 for storing prohibiting/enabling status receiving all of the interrupt requests, and instruction execution control unit 114 controls so that becomes enabling when an request having priority level received prohibiting no received. Hence, requests levels, high can be immediately without via status. For it possible to receive higher such as debugger like, unnecessary perform multi-interrupt processing.
google.de 参考文章(11)
James E. Hodge, Multi-level priority micro-interrupt controller ,(1984)
Brent C. Beardsley, Cortland D. Starrett, John R. Wolfe, David L. Leigh, Method and system for the efficient response to multiple different types of interrupts ,(1992)
Robert E. Garner, Robert B. Cohen, Method and apparatus for preventing recursion jeopardy ,(1990)
Karl W. Stevens, Carl H. Grant, Robert L. Adams, I/O Interrupt sequencing for real time and burst mode devices ,(1978)
Joseph M. Lamb, Programmable interrupt priority encoder method and apparatus ,(1992)
Kenneth C. Klingman, Jon Rubinstein, System for assigning interrupts to least busy processor that already loaded same class of interrupt routines ,(1988)
John M Loffredo, Larry E Wise, Michael I Davis, Patrick L Rickard, Data acquisition and control system including dynamic interrupt capability ,(1974)
Gerald Paul Braunstein, Fixed priority interrupt control circuit ,(1975)
Sachiko c, Tsuyoshi C, Interrupt control unit ,(1992)