作者: Lei Luo , Song Chen , Minchao Zhou , Tianfeng Ye
DOI: 10.23919/VLSIC.2017.8008507
关键词:
摘要: A 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration is presented. 10% of the area utilized for interleaving mismatch estimation and correction. The achieves −64dB spur 50.1dB SNDR at Nyquist rate, 10.4mW power consumption 0.014mm2 in 16nm.