Logic state analyzer

摘要: Clock signals, data words and qualifier signals are received via monitor probes during a acquisition mode, selected being stored in memory response to the clock signals. The may then be displayed tabular or map format on cathode ray tube screen. Data acquired randomly, i.e., free-running sampling selectively by using pattern recognition delay trigger circuits. Using display format, as ones zeroes. each word thus is CRT screen dot subsequent mode. position of uniquely identifies its address state value. most significant bits determine vertical least horizontal dot. intensity indicates relative frequency occurrence that logic state. A trace between dots utilized vector indicate sequence which acquired, brightened intensified end indicating direction. vectors non-linear so when flow occurs opposite directions states, will not overlap obscure useful information. cursor provided select area an expanded wherein portion larger scale. Also, comparator mode allow comparison input with auxiliary memory.