Direct digital synthesizer based on delay line with sorted taps
作者： David E. Bockelman
DOI:
关键词:
摘要: A digital frequency synthesizer includes a clock which produces signal oscillating at fixed and delay line receives the therefrom plurality of phase shifted signals frequency. Each is in with respect to other signals. look-up table an address value related ideal outputs tap value. selection circuit one response thereto. sampling samples least portion output by sampled form part oscillator having desired
lens.org 参考文章(10)
Laurence D. Lewicki, Kern Wai Wong, Pak-Ho Yeung, Phase locked loop fractional pulse swallowing frequency synthesizer ,(1996)
Yido Koo, Joon-Young Park, Joonbae Park, Wonchan Kim, A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method international conference on vlsi and cad. pp. 339- 341 ,(1999) , 10.1109/ICVC.1999.820925
Kevin McCall, Ronald Kroesen, Janos Kovacs, Dynamic phase selector phase locked loop circuit ,(1995)
Didier Valenti, Alain Vergnes, Frequency synthesis circuit tuned by digital words ,(1999)
Jeffrey D. Currin, D. James Chapman, Calibratable programmable phase shifter ,(1998)
Charles M. Puckette, Digitally programmable phase shifter ,(1979)
Stanley R. Zepp, Adjustable phase clock circuit using the same and related methods ,(1998)
Gerhard Wischermann, Digital oscillator for generating a signal of controllable frequency ,(1991)
Gary J. Lesmeister, Self-calibrating programmable phase shifter ,(1999)
Glenn B. Dixon, Apparatus and method for fractional frequency division ,(1991)