A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system
作者： Aniruddha Ghosh , Satrughna Singha , Amitabha Sinha
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摘要: Execution of arithmetic operations at very high speed in real time is the major concern digital signal processing (DSP) because DSP algorithms are computation intensive. In recent times, Residue Number Systems (RNS) considered as alternative to binary number system their capabilities performing "carry-free" addition and Multiplication. Double Base (DBNS), another non-binary systems also increasingly becoming attractive for applications due handling operations, particularly multiplication efficiently. However, complexity involved converting DBNS becomes a bottleneck efficiency performance decreases considerably large conversion time. So RNS Adder Multiplier can be used implement multiply & accumulate (MAC) units. Because adders less complex faster compared multipliers efficient multiplier. MAC units key Digital Signal Processors. this paper we have shown how FIR filter implemented using proposed "Mixed System units".
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