A 32-bit SoPC implementation of a P/sup 5/

摘要: This paper details a system on programmable chip (SoPC) implementation of 2.5 Gbps point-to-point-protocol processor (P/sup 5/) an FPGA. 32-bit pipelined PPP receiver and transmitter dedicated packet circuits are implemented. The Leon core is embedded in the provides platform for control protocols including LCP's NCP's application specific software. An AMBA bus interface used to interlink hardware processing unit presents standard allowing easy retargeting other platforms. Complex memory implemented enable microprocessor handle extreme data rate P/sup 5/. high-level breakdown described synthesis results Altera FPGA technology presented.