High speed image processing computer

摘要: An image processor having an algorithm (66) operating under control of a writable store (94), and number parallel processors (72) instruction words from (100). memory controller (68) receives addresses the for coordinating reading writing (82) using pixel data processed by set (72). The arbitrates address request cycles, refresh cycles screen cycles. includes different planes (84, 86 88) assocated with red, green blue data. Associated each plane is video (106) converting to high speed serial output further through look-up tables (108) provide color signals monitor (28). Overlay stored in overlay (90), associated (80) (116). Mask generated mask coupled masking one or more pixels multi-pixel word individual bits within said pixels.