Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS microstrip line model
作者： H. Hasegawa , S. Seki
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摘要: Using an MIS (metal-insulator-semiconductor) microstrip-line model for interconnection and its equivalent circuit representation, on-chip delay in very high-speed LSI/VLSI's is analyzed the time domain, changing geometry, substrate resistivity, terminal conditions. The results show following: 1) "lumped capacitance" approximation inapplicable interconnections (t pd of below 100-200 ps); 2) as compared to semi-insulating substrate, presence slow-wave mode transition semiconducting substrates causes 1.5-2 times increase 2-10 rise time; 3) order realize propagation less than 100 ps per gate at LSI/VLSI levels, effective signal source resistance should be 500 Ω so long interconnections.
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