Clock dejitter circuits for regenerating jittered clock signals.

摘要: Clock dejitter circuits are provided and comprise control (30) for generating a plurality of pulses over clock cycle, (60) tracking the speeds jittered incoming data signal based on those speeds, utilizing pulses, substantially unjittered signals at nominal rates signals. A circuit broadly includes divide by value x-divide x+1 (42) which receives fast input signal, modulus y counter (46), count decode (52) providing z y, logic gate (56) taking outputs from controlling block to guarantee that divides x q times every r x+1; wherein plus equals either q+1 or r+1.