An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization

摘要: We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed create accurate time breakdown Weibull distribution. The proposed also facilitates investigations any spatial correlation failures, and can monitor progressive decrease in resistance. Measurement results presented from 32 × array implemented 130-nm bulk CMOS process. Results show that system capable taking measurements across range voltages temperatures, which critical extrapolating accelerated stress experiment expected device lifetimes under realistic operating conditions.