A generic CAD tool for efficient NoC design

摘要: Network on chip (NoC) using packet switching is a solution to cope with complex system (SoC) communications. However, tools are needed help designers deal NoC. The two elements composing an NoC its routers and network interfaces (NI). We focus the specification generation steps of /spl mu/spider NOC design flow that addresses what we consider as main features realistic useful Firstly, synthesis tool based generic router through user friendly interface. Secondly, it supports management different levels quality service (QoS), allowing guaranteed throughput (GT) in addition classical best effort (BE) service. Finally, can be tuned handle asynchronous paper presents architecture various custom characteristics. show tradeoff between hierarchical QoS channel implementation performance system.