Vector processor with vector data compression/expansion capability

摘要: A vector processor comprises a memory (1) for storing data, plurality of registers each capable reading or writing plural (m) elements in parallel, at least one mask register (4) m bits transfer portion (2, 2-0, 2-1, 2-2, 2-3) connected to the memory, and responsive an instruction transferring from regularly spaced address locations within selected storage corresponding valid bits. The includes count (307) counting total number already read out access (300 306, 308, 310 2-i (i=0 - 3)) operable concurrently means validness currently bits, invalid included having preceding sequential numbers element that bit counted generating location which hold be transferred should receive location.