Integrating analog to digital converter with improved resolution

摘要: An analog to digital (A/D) converter system and method which provides improved resolution reduced noise for integrating-type ADCs, including dual slope, multi sigma-delta type A/D converters. After the ramp-up interval of either a slope or integrating converter, ramp-down occurs, wherein reference signal is then applied integrator return its original value. The clock cycles are counted while voltage determine primary count During interval, applied, two more voltages measured. In one embodiment, first measured before value second after value, e.g., zero crossing. determines fractional based on voltages, i.e., occurring determined by extrapolating interpolating using voltages. total calculated counts, output