A cyclic A/D converter that does not require ratio-matched components
作者： H. Onodera , T. Tateishi , K. Tamaru
DOI: 10.1109/4.272
关键词:
摘要: The circuit configuration of a cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is described. analog portion the consists two operational amplifiers, four capacitors, and ten switches regardless number bits per sample converted, completes an n-bit conversion in 3n clock cycles. characteristics are inherently insensitive both to capacitor ratio amplifier offset voltage. circuit, therefore, can be realized small die area. effects finite gain switch charge injection on accuracy discussed. A prototype chip has been fabricated 2- mu m CMOS technology operating single 5-V supply. When it operated as 8-bit at sampling rate 8 kHz, maximum error 0.2 LSB (least-significant bit) for differential nonlinearity 0.5 integral nonlinearity. area measures 0.79 mm/sup 2/. >
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