Phase-Locked Loop Synthesizer Simulation

摘要: Phase locked loops (PLLs) are electronic circuits that ensure a communications signal stays on given frequency. Their design is crucial to the workings of wireless systems. Virtually all transceivers use PLLs synthesize stable, high frequency oscillations necessary for radio & wireless. This book describes how calculate PLL performances by using standard mathematical or circuit analysis programs. Theoretical descriptions limited minimum needed explain perform calculations. Although presented methods can be implemented with many commercial programs, their description always refers Mathcad and SIMetrix. Table contents Preface Chapter 1: Phase-Locked Loop Basics 1.1 Introduction 1.2 Working Principles 1.3 Laplace Fourier Transforms 1.3.1 Definitions 1.3.2 Basic properties 1.3.3 some important functions 1.4 Transfer Functions 1.4.1 stability 1.5 Order Type 1.6 First-Order 1.7 Second-Order 1.8 References 2: Components 2.1 2.2 Detector 2.2.1 Multiplier as phase detector 2.2.2 2.3 Filter 2.3.1 Reference spur filtering 2.3.2 filters voltage output detectors 2.3.3 charge pump 2.3.4 filter scaling 2.4 VCO 2.4.1 Principle working 2.4.2 2.4.3 Noise 2.4.4 Pulling pushing 2.5 Sources 2.6 Frequency Dividers 2.6.1 divider noise 2.7 3: Fractional-N Divider 3.1 3.2 Single-Accumulator Fractional 3.3 Multiple-Accumulator 3.3.1 Z transform 3.3.2 First-order _-_ modulator 3.3.3 Higher-order converters 3.3.4 Multiple-accumulator fractional-N 3.4 4: Synthesizer Performance Simulation 4.1 4.2 Techniques 4.3 4.3.1 4.3.2 synthesizer 4.4 Modulation 4.4.1 reference oscillator only 4.4.2 4.4.3 Dual-point modulation 4.5 Settling Time 4.5.1 Lock-in 4.5.2 Pull-in 4.6 Final Note Circuit-Based 4.7 5: Miscellaneous 5.1 5.2 Verification 5.2.1 Measurement response magnitude 5.3 Sampling 5.4 Multiple-Loop 5.4.1 multiple-loop 5.4.2 Transients in 5.4.3 Variations double-loop architecture 5.5 Direct Digital 5.5.1 DDS operation 5.5.2 Effects nonideal components performance 5.5.3 Enhancements 5.6 Index