Mixing Synchronous Reactive and Untimed MoCs in SystemC

摘要: The support of heterogeneity at the specification level, i.e., ability to mix several models computation (MoCs) in system-level specification, is becoming increasingly important design methodologies hardware/software (HW/SW) embedded systems. It presents advantages. At modeling it enables a more natural description that can be efficiently simulated. In addition, ease automation flow over heterogeneous target platform. This work context development methodology based on SystemC. able untimed MoCs (such as process network (PN), Kahn (KPN), and communicating sequential (CSP)) with detailed handling time, such synchronous reactive (SR) MoC. problem MoC interfaces has been addressed specifically solved for untimed–untimed interfaces. this chapter, extended connection between SR involves intersection different restrictions time domain. way which untimed–SR interface specifies how events map onto domain shown. These general concepts are reflected later SystemC interfaces, consisting border processes channels. incompatibilities provoked or transmitted by also shown, well these detected Previously, study semantics assumptions abstracted from model presented.