Frequency counter and method of counting frequency of a signal to minimize effects of duty cycle modulation

摘要: A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a (50) includes first (52) that accumulates reference clock pulses between successive rising edges an input signal. An signal is also applied to inverter (54), which inverts square wave prior applying it second (56) cycles inverted sensor summation junction (60) totals accumulated counts from counters so they can be averaged by divider (62), divides total count two. The technique employed in connection with integer (72) totaling number occurring during sample time defined gate signals.