Evaluation of granularity on threshold voltage control in flex power FPGA

作者: Masakazu Hioki , Takashi Kawanami , Toshiyuki Tsutsumi , Tadashi Nakagawa , Toshihiro Sekigawa

DOI: 10.1109/FPT.2006.270386

关键词:

摘要: The flex power FPGA can flexibly control speed and in a trade-off relationship by flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static consumption an area-overhead the on various granularity FPGA. There is also between for granular voltages. Both grain size its style division have strong influence trade-off. Own evaluation results show that reduces less than 1/5 original level, while increase area overhead 40%. If 50% allowed, then reduction 1/10 or obtained

参考文章(18)
J.H. Anderson, F.N. Najm, Low-power programmable routing circuitry for FPGAs international conference on computer aided design. pp. 602- 609 ,(2004) , 10.1109/ICCAD.2004.1382647
Alexander Marquardt, Vaughn Betz, Jonathan Rose, Architecture and CAD for Deep-Submicron FPGAS ,(1999)
Toshihiro Sekigawa, Takashi Kawanami, Toshiyuki Tsutsumi, Masakazu Hioki, Hanpei Koike, Hiroshi Nagase, Tadashi Nakagawa, Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity IEICE Transactions on Information and Systems. pp. 2004- 2010 ,(2004)
Tim Tuan, Arif Rahman, Satyaki Das, Steve Trimberger, Sean Kao, A 90-nm Low-Power FPGA for Battery-Powered Applications IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 26, pp. 296- 300 ,(2007) , 10.1109/TCAD.2006.885731
Arifur Rahman, Vijay Polavarapuv, Evaluation of low-leakage design techniques for field programmable gate arrays field programmable gate arrays. pp. 23- 30 ,(2004) , 10.1145/968280.968285
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity field programmable gate arrays. pp. 257- 257 ,(2004) , 10.1145/968280.968351
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai, A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme international solid-state circuits conference. ,vol. 31, pp. 1770- 1779 ,(1996) , 10.1109/JSSC.1996.542322
S. Borkar, Low power design challenges for the decade asia and south pacific design automation conference. pp. 293- 296 ,(2001) , 10.1109/ASPDAC.2001.913321
Tim Tuan, Sean Kao, Arif Rahman, Satyaki Das, Steve Trimberger, A 90nm low-power FPGA for battery-powered applications field programmable gate arrays. pp. 3- 11 ,(2006) , 10.1145/1117201.1117203