A High Power Low Dropout Voltage Regulator Design with an Enhanced Resistive Bank Circuit for Powering an RF IC for DSRC Applications

摘要: This paper presents a high power Low Dropout Voltage Regulator Design with an enhanced resistive bank circuit for powering RF IC DSRC applications. Due to the addition of resistor circuit, feedback takes part in amplified output from input, such that gain is controlled much more by network. A low pass filter used remove excess noise. The quiescent current proposed LDO structure reduced 3.85 µA 3.3 V supply voltage, improve efficiency LDO. Phase Margin bandgap reference 62.30°. For load 100 mA settling time 26 µs achieved PSRR -46 dB till 1 kHz frequency. Line regulation and Load 30.6 mV/V 0.278 mV/mA respectively. implemented using 130 nm Bipolar-CMOS-DMOS (BCD) technology active area 206 µm X 161 µm.