The effect of logic block architecture on FPGA performance

摘要: This authors explore the effect of logic block architecture on speed a field-programmable gate array (FPGA). Four classes are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each set benchmark circuits synthesized into FPGAs that use different blocks. The resulting FPGA implementations using measured. While results depend delay programmable routing, experiments indicate five- six-input tables certain configurations produce lowest total over realistic values routing delay. fine grain blocks, such as two-input gate, exhibit poor performance because these gates require many levels to implement hence large >