Broadband high level data link communication line adapter

摘要: A hardware/firmware communication line adapter for interfacing a processor to broadband high level data link channel. Transmit and receive control characters received either from the or channel device are processed under of firmware effectuate CRC checking, byte size control, extended variable field format partial last block transfer functions on transmitted/received stream. First-in-first-out (FIFO) buffer memories employed in transmit circuits queue frame at whereby processor/adapter interface is simplified. Similarly, FIFO reduce frequency interrupts enable processor.