Energy efficient interface circuits between adiabatic and standard CMOS logic at 90 nm technology

摘要: Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The saving of adiabatic circuit can reach more than 90% compared conventional static logic. clocking schemes signal waveforms different from those circuits. This paper investigates the design approaches low-power interface terms energy dissipation. Several that convert signals between presented. With BSIM 3v3 90 nm technology, consumption proposed has relatively large over wide range frequencies. also delay product supply voltages. Simulation been done on tanner EDA tool at 90nm technology.