A low-power high-performance digital circuit for deep submicron technologies

摘要: This paper presents a novel digital circuit design methodology that can support high-performance and low-power applications. In this method, reusing past internal voltages, signals are charged to Vdd/2 during the pre-charge cycle, so voltage of signal is changed by just evaluation resulting in significant reduction power consumption propagation delay. The simulation results performed 0.18/spl mu/m CMOS technology, demonstrate new has three times improvement terms delay comparison equivalent domino dynamic logics. More importantly, its 2.4 less than logics counterpart.