A complementary low power non-volatile reconfigurable eecell
作者： Richard G. Cliff , John E. Turner
DOI:
关键词:
摘要: A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. inverter formed by fabricating an n-channel MOSFET and p-channel with merged floating gate regions. tunnel capacitor allows charge to be supplied or removed from the gate. The provides storage. senses presence absence of on amplified inverted output. consumes very low power rail-to-rail output voltage swings.
google.de 参考文章(6)
Vikram Kowshik, Elroy M. Lucero, Zero power, electrically alterable, nonvolatile latch ,(1989)
Michael S. Briner, Nader A. Radjy, Optimized electrically erasable cell for minimum read disturb and associated method of sensing ,(1990)
Daniel Harrison Bennett, Kenelm Gerald Digby Murray, Gary Lawrence Dodd, A non-volatile ram bit cell ,(1990)
Emanuel Hazani, E2 prom cell including isolated control diffusion ,(1989)
Dhaval J. Brahmbhatt, Improved logic cell array using CMOS E2 PROM cells ,(1987)
Kouji Sekiguchi, Non-volatile memory device ,(1990)