Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)

摘要: The proposed architecture is integrated onto a Digital Signal Processor (DSP) as coprocessor to assist in the computation of sum absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with downsampling (or upsampling) option, Discrete Cosine Transform (DCT)/Inverse (IDCT), and generic algebraic functions. called IPP, which stands for image processing peripheral, consists 8 multiply-accumulate hardware units connected parallel routed multiplexed together. can be dependent upon Direct Memory Access (DMA) controller retrieve write back data from/to DSP memory without intervention from core. set up DMA transfer IPP/DMA synchronization advance, then go on its own task. Alternatively, perform transfers itself by synchronizing IPP these transfers. This implements 2-D filtering, short filters, mosaic decoding more efficiently than previously disclosed architectures prior art.