Partition-Based Hardware Transactional Memory for Many-Core Processors

摘要: Transactional memory is an appealing technology which frees programmer from lock-based programming. However, most of current hardware transactional systems are proposed for multi-core processors, and may face some challenges with the increasing processor cores in many-core systems, such as inefficient utilization buffers, unsolved problem buffer overflow, etc. This paper proposes PM_TM, a processors. The system turns buffers that traditionally private to into shared by moving them L1-level L2-level, uses partition mechanism provide logically independent dynamically expandable threads. As result, solution can utilize more efficient moderate overflow. simulated evaluated using gems simics simulator STAMP benchmarks. Evaluation results show achieves better performance scalability than traditional solutions