Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic

摘要: Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to small set computational problems due lack flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations redefined even at run time. In this context, several alternative architectures explored powerful tools are needed model evaluate them. We show how well-known rewriting-logic environments could used quickly simulate complex application specific digital systems speeding-up its subsequent prototyping. use which applied efficient treatment dynamic programming methods for resolving such as global local sequence alignment (Smith-Waterman algorithm), approximate string matching computation longest common subsequence. A VHDL description conceived architecture was implemented from based abstract models synthesized over an FPGA APEX family.