Temporally redundant latch for preventing single event disruptions in sequential integrated circuits

摘要: A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent which a correct sample can be selected. The has three sampling circuits (e.g., D flip-flops DICE latches) that the different and distinct times. also release coupled select majority of collected by fourth time again is affords both spatial parallelism due parallel temporal resulting clocking scheme involving time-spaced clock signals. immune upsets might occur itself, as well any control signals on IC device.