FPGA-based configurable systolic architecture for window-based image processing

摘要: Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware improve execution time achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The on a 2D array 7×7 window processors. was implemented an FPGA to execute algorithms with sizes up 7×7, but the design scalable cover larger if required. reaches 3.16 GOPs at 60 MHz clock frequency 8.35 milliseconds generic operators 512×512 gray-level images. compares favorably other architectures terms utilization. Theoretical experimental results are demonstrate effectiveness.