High-Level Simulation for Spiking Neuromorphic Computing Systems

作者: Nicholas D. Skuda , Catherine Schuman , Gangotree Chakma , James S. Plank , Garrett S. Rose

DOI: 10.1109/ISCAS.2018.8351840

关键词:

摘要: Neuromorphic computing systems are alternatives to conventional microprocessors, often built from unconventional hardware. Designing and evaluating these requires multiple levels of simulation, the device level circuit system level. In this paper, we describe simulator a neuromorphic based on memristors. We compare it same system, both verifying its accuracy demonstrating performance improvement. argue that simulation is an essential part design process systems.

参考文章(21)
Robin B. Jacobs-Gedrim, Sapan Agarwal, Kathrine E. Knisely, Jim E. Stevens, Michael S. van Heukelom, David R. Hughart, John Niroula, Conrad D. James, Matthew J. Marinella, Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator 2017 IEEE International Conference on Rebooting Computing (ICRC). pp. 1- 10 ,(2017) , 10.1109/ICRC.2017.8123657
James S. Plank, Garrett S. Rose, Mark E. Dean, Catherine D. Schuman, Nathaniel C. Cady, A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications 2017 IEEE International Conference on Rebooting Computing (ICRC). pp. 1- 8 ,(2017) , 10.1109/ICRC.2017.8123655
Marta Kolasa, Rafal Dlugosz, An advanced software model for optimization of self-organizing neural networks oriented on implementation in hardware international conference mixed design of integrated circuits and systems. pp. 266- 271 ,(2015) , 10.1109/MIXDES.2015.7208524
William P. Risk, Theodore M. Wong, Horst D. Simon, Steven K. Esser, Dharmendra S. Modha, Raghavendra Singh, Robert Preissl, Pallab Datta, Myron Flickner, Compass: a scalable simulator for an architecture for cognitive computing ieee international conference on high performance computing data and analytics. pp. 1- 11 ,(2012) , 10.5555/2388996.2389070
Sung Hyun Jo, Ting Chang, Idongesit Ebong, Bhavitavya B. Bhadviya, Pinaki Mazumder, Wei Lu, Nanoscale Memristor Device as Synapse in Neuromorphic Systems Nano Letters. ,vol. 10, pp. 1297- 1301 ,(2010) , 10.1021/NL904092H
Giacomo Indiveri, Bernabé Linares Barranco, T Masquelier, María Teresa Serrano Gotarredona, T Prodromakis, None, STDP and STDP variations with memristors for spiking neuromorphic learning systems. Frontiers in Neuroscience. ,vol. 7, pp. 2- 2 ,(2013) , 10.3389/FNINS.2013.00002
Mohamed Khalil-Hani, Vishnu P. Nambiar, M. N. Marsono, Co-simulation methodology for improved design and verification of hardware neural networks conference of the industrial electronics society. pp. 2226- 2231 ,(2013) , 10.1109/IECON.2013.6699477
O. Bichler, D. Roclin, C. Gamrat, D. Querlioz, Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator international symposium on nanoscale architectures. pp. 7- 12 ,(2013) , 10.1109/NANOARCH.2013.6623029
Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart, R. Stanley Williams, The missing memristor found Nature. ,vol. 453, pp. 80- 83 ,(2008) , 10.1038/NATURE06932
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, Jose A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman, A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons custom integrated circuits conference. pp. 1- 4 ,(2011) , 10.1109/CICC.2011.6055293