A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding

摘要: Bioengineering research is posing hard challenges to digital embedded system designers. Tight real-time constraints, miniaturization, and low power are critical issues exacerbated by applications requiring the implant of electronic devices in patient's body. Among them, neurocontrolled motor prostheses on cutting edge field, neural signal decoding extract movement intention order control mechatronic device. Despite literature how implement a highly-portable reliable integrated platform still an open question. In this paper, we propose field-programmable gate array-based prototype multi-processor system-on-chip architecture that implements online algorithm. The capable respecting constraints posed application when clocked at less than 50 MHz. Considering workload extremely data dependent unpredictable, has be dimensioned taking into account worst-case operating conditions ensure robustness. To compensate resulting over-provisioning architecture, software-controllable management been integrated. Experimental results demonstrate behavior allow evaluating usefulness proposed technique public databases.