Method and apparatus for implementing fault tolerant phase locked loop (PLL)
作者： Eugene Nosowicz
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摘要: A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes divide by N defined plurality of sub-divide functions, each providing feedback frequency signal applied to voter circuit. provides an output based upon majority vote the functions.
lens.org 参考文章(9)
Shuran Wei, Randy Tsang, Voltage control oscillator noise reduction technique and method thereof ,(2002)
Afshin Momtaz, Germain Gutierrez, GM cell based control loops ,(2002)
Koju Aoki, Hiroyuki Sakima, Mode switching method for PLL circuit and mode control circuit for PLL circuit ,(2002)
Ola Per Martinsson, Stefan Hans Bertil Davidsson, Carl Michael Carlsson, A hardware design for majority voting, and testing and maintenance of majority voting ,(1998)
Rahul S. Majumdar, Radiation hard divider via single bit correction ,(2001)
Chamath Abhayagunawardhana, David S. Dunning, Richard S. Jensen, Kenneth Drottar, Differential simultaneous bi-directional receiver ,(2000)
Stephen M. Trimberger, Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices ,(2004)
Kirk Kohnen, Triple redundant self-scrubbing integrated circuit ,(2001)
Morihito Hasegawa, Low power prescaler for a PLL circuit ,(1998)