FPGA-friendly code compression for horizontal microcoded custom IPs

摘要: Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meeting timing constraints of automatically generated IPs is often a challenging time-consuming task must be repeated every time the specification modified. To address this issue, new generation IP-design technologies capable generating custom datapaths as well programming an existing one developed. These are based on Horizontal Microcoded Architectures. Large code size well-know problem in HMAs, referred "code bloating" problem.In paper, we study HMA-based called NISC. We show NISC can several times larger than typical RISC processor, propose low-overhead dictionary-based compression techniques reduce size. Our algorithm leverages knowledge "don't care" values control words better compress content dictionary memories. experiments by selecting proper memory architectures reduced 70% (i.e. 3.3 times) at cost only 9% performance degradation. also some may increase number utilized block RAMs FPGA-based implementations. combining dictionaries implementing them using embedded dual-port